NBTI - aware Dual V th Assignment for Leakage Reduction and Lifetime Assurance ∗

Negative bias temperature instability (NBTI), which causes temporal performance degradation in digital circuits by affecting PMOS threshold voltage, has become the dominant circuit lifetime reliability factor. Design for lifetime reliability, especially for NBTI-induced circuit performance degradation, is emerging as one of the major design concerns. In this paper, an NBTI-aware dual Vth assignment is for the first time proposed to simultaneously reduce the circuit leakage current and ensure the circuit lifetime requirement. Our experimental results on ISCAS85 benchmark show that the NBTI-aware dual Vth assignment not only assigns more high Vth gates in the ISCAD85 circuits and leads to up to 14.88% (average 3.46%) further leakage saving under 5% circuit performance relaxation, but also brings different optimal high Vth (on average 11mV higher) without performance relaxation.